Most VLSI (very large scale integrated) circuits may have embedded memory arrays. Total size of these memories may range within certain limits (e.g., from 3 to 80 megabits) and/or may have defined range of instances (e.g., over 600 instances) of such memories of an ASIC (application specific integrated circuit) device. Design effort and/or silicon overhead for a design for test (DFT) of VLSI circuits have become a significant part of semiconductor chip design. Unlike memory ICs, embedded memory ports may not have a privilege of direct access through integrated circuit (IC) pins. This may result in use of BIST (Built-In -Self Test) as a widely accepted on-chip memory test solution. There may b e many variants of BIST based on capability and/or features.
In all cases, outputs may be tested against expected outputs and may place a requirement for the BIST to produce and/or synchronize expected versus actual memory test outputs. For wide-word width memories, outputs may need to be sliced into smaller segments to fit within the BIST comparator's data bandwidth. In order to complete the test, repeated read cycles may be necessary to cover all the outputs. Multiplexers may be needed to select an appropriate output segment of the memory for a compare function.
Timing closure may be a big challenge for ICs with large members of embedded memory arrays, along with reduction of silicon area for BIST. Other problems in conventional use of BIST in complex VLSI circuits may include complex read architecture, backward data path to the controller for feeding the outputs for compare and/or large product design cycle times due to a need for extensive timing verification.